Intel Battles AMD With Multicore CPU Road Map Changes

Santa Clara, Calif.-based Intel said last week it will replace a multiprocessor platform scheduled for 2007 called Reidland with a new platform that will provide a dedicated bus from each CPU to the Northbridge chipset.

In current Intel designs, all the CPUs share one connection to the chipset, called a front-side bus. That can cause bottlenecks in memory and I/O, two key areas controlled by the chipsets. Intel has been criticized by server makers for its memory architecture. While AMD integrates a memory controller directly into its CPU to increase performance, Intel&'s systems use the shared front-side bus to connect with memory.

An Intel spokesman said the new platform, code-named Caneland, was not developed specifically to address memory bandwidth issues. He said Intel is integrating more cache onto the CPU to address that issue.

However, many industry observers have speculated that Caneland is a response to Intel&'s memory problems. “The immediate advantage is the memory bandwidth because the Northbridge connects to the memory,” said Tau Leng, director of marketing at system builder Supermicro, San Jose, Calif.

The Intel spokesman said Caneland will support a CPU, code-named Tigerton, that will contain at least four cores, another reason a dedicated connection to the chipset is important.

AMD, meanwhile, has pinpointed 2008 as the year it is looking at multicore—that is, more than two cores—processors.

In addition to the changes to its x86 server platform, Intel noted that the next-generation chip in its troubled Itanium processor line will be delayed by up to three months. The Montecito CPU, initially expected to debut late this year, is now slated for 2006 due to “quality” concerns, the spokesman said.

That chip also is losing a feature that can detect if extra processing cycles are available and can apply them in realtime. The feature will be available in a future Itanium version.